SRF Technologies, LLC

Founded in April 2006 by Stephen Fairbanks, SRF Technologies is dedicated to supplying its customers the expertise needed to develop in-house ESD and I/O capabilities not typically available to small and start-up companies in the semiconductor industry.

We specialize in both ESD diagnostic and failure-analysis support, recognizing that such efforts can take months and cost tens of thousands of dollars.  By employing SRF Technologies, our customers have dramatically improved their debug time as well as getting the right solution at the first redesign, saving both money and time to market.

Besides ESD failure analysis and diagnostic support, our primary areas of expertise lie in ESD design for RF and analog products, as well as very large and complex SoC's involving many domains (>30). 

Extensive experience in designing ESD and I/O's to not only meet ESD requirements, such as CDM (Charge-Device Model), HBM (Human Body Model), MM (Machine Model) and CDE (speculative Cable Discharge Models), but also the rigorous demands of DFM (Design for Manufacturing), SI (signal integrity) and power delivery as they become larger and larger problems at 65nm and below.

SRF Technologies is a valuable resource to many companies looking to address these issues in a cost effective and efficient manner.

Stephen Fairbanks

With nearly a decade of experience designing systems and products to interface to each other while withstanding the rigors of ESD and EMI susceptibility, Stephen brings a unique and honed skill set that his customers can leverage.

In the semiconductor industry, he has been developing process specific I/O and ESD libraries for 6 years. Most notably are his efforts at Intel Corporation where he was the lead developer of the ESD and I/O libraries used on 3 generations of the wireless components (MAC basebands and RF Front Ends) of the Intel Centrino chipsets. He was also personally responsible for the ESD development and I/O support for 3 families of cellular communications processors and 4 families of handheld applications processors. He has developed ESD process design rules, ESD libraries, and IO libraries in 0.13μm RF, 0.13μm mixed-signal, 90nm mixed-signal, 90nm low power and 65nm low power processes. Stephen gained further experience supporting ESD development on several Flash memory processes. He has personally designed/co-designed padrings for 7 products currently in high volume manufacturing including Radio Frequency Front Ends (RFE’s), Analog Front Ends (AFE’s) and Applications Processors for the PDA/cellular industry. Looking forward, he was very involved in the ESD protection strategies for Intel’s High-Speed digital pins including ESD protection for PCI-Express, SATA and Intel’s future CSI interface. Previous to Intel he developed data acquisition systems for the scientific instrumentation industry, specializing in Mass Spectrometers. He interned at Iomega early in his career developing translation cards for 1394 (Firewire), SCSI and ATAPI interfaces. He has a BSEE with a minor in mathematics from Brigham Young University and has taken graduate level courses in electrical engineering from Stanford and UC Berkeley.